Asynchronous component implementation methodology for GALS design in FPGAs

A methodology for implementing GALS design in conventional FPGAs using existing tools is presented. The goals were to define the minimal set of basic asynchronous components, to examine the methodology of their implementation and to establish the design constraints and limitations of such circuits. Simulation results confirm that GALS designs implemented using the Look-Up Table or the Flip-Flop with Place & Route tools and asynchronous components such as the delay element, the Muller-C element or the arbiter are supported by conventional synchronous FPGAs as long as these designs are implemented within suitable constraints and operated within circuit limitations.