Title :
A new methodology for the design of asynchronous digital circuits
Author :
Nanda, E. ; Desai, S.K. ; Roy, S.K.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Kanpur, India
Abstract :
This paper discusses a new design methodology for asynchronous digital circuits. The methodology is based on an event driven scheme and follows the double-rail logic handshake protocol. A new logic gate, called the Universal Gate, is designed; this is the basic building block of the methodology. It is shown that the methodology, is completely delay insensitive. As an example, the Shift Multiplier is implemented
Keywords :
Boolean functions; asynchronous circuits; combinational circuits; digital integrated circuits; integrated logic circuits; logic design; logic gates; protocols; asynchronous digital circuits; delay insensitive design; design methodology; double-rail logic handshake protocol; event driven scheme; logic gate; shift multiplier implementation; universal gate; Asynchronous circuits; Clocks; Design methodology; Digital circuits; Logic design; Logic devices; Logic gates; Protocols; Throughput; Wires;
Conference_Titel :
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location :
Hyderabad
Print_ISBN :
0-8186-7755-4
DOI :
10.1109/ICVD.1997.568101
