On the automatic integration of hardware accelerators into FPGA-based embedded systems

Author

Pilato, Christian ; Cazzaniga, Andrea ; Durelli, Gianluca ; Otero, Andres ; Sciuto, Donatella ; Santambrogio, Marco D.

Author_Institution

Dipt. di Elettron. ed Inf., Politec. di Milano, Milan, Italy

fYear

2012

fDate

29-31 Aug. 2012

Firstpage

607

Lastpage

610

Abstract

This paper proposes an automatic framework for the seamless integration of hardware accelerators, starting from an OpenMP-based application and an XML file describing the HW/SW partitioning. It extends a fully software architecture by generating and integrating the cores, along with the proper interfaces, and the code for scheduling and synchronization. Experimental results show that it is possible to validate different solutions only by varying the input code.

Keywords

XML; application program interfaces; electronic design automation; embedded systems; field programmable gate arrays; hardware-software codesign; software architecture; FPGA-based embedded systems; HW-SW partitioning; OpenMP-based application; XML file; automatic framework; automatic hardware accelerator integration; hardware-software partitioning; scheduling code; software architecture; synchronization code; Computer architecture; Field programmable gate arrays; Hardware; Program processors; Resource management; XML;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on

Conference_Location

Oslo

Print_ISBN

978-1-4673-2257-7

Electronic_ISBN

978-1-4673-2255-3

Type

conf

DOI

10.1109/FPL.2012.6339218

Filename

6339218