DocumentCode
1947471
Title
Asynchronous implementation of synchronous Esterel specifications
Author
Mitra, Raj S. ; Bhattacharya, Bishnupriya ; Lavagno, Luciano
Author_Institution
Cadence Design Syst. Pvt. Ltd., Uttar Pradesh, India
fYear
1997
fDate
4-7 Jan 1997
Firstpage
348
Lastpage
353
Abstract
The synchrony hypothesis of Esterel demands the generation of a single monolithic FSM from the specifications. However for large specifications, the size of this FSM can prove to be inhibitively large. In this paper, we propose a practical solution to this problem, which generates separate FSMs for each of the concurrent instructions. We also enumerate the deviations in semantics due to this translation algorithm so that the user is aware of the executable semantics that he should expect
Keywords
asynchronous circuits; finite state machines; logic CAD; software engineering; specification languages; FSM generation; asynchronous implementation; concurrent instructions; executable semantics; hardware-software codesign; large specifications; separate FSMs; synchronous Esterel specifications; translation algorithm; Broadcasting; Circuit synthesis; Delay; Embedded software; Embedded system; Hardware; Integrated circuit interconnections; Merging; Software systems; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1997. Proceedings., Tenth International Conference on
Conference_Location
Hyderabad
ISSN
1063-9667
Print_ISBN
0-8186-7755-4
Type
conf
DOI
10.1109/ICVD.1997.568106
Filename
568106
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