Fault test structures for studying circuit performance

Testing of ASICs is usually limited to “stuck-at” fault testing, and the consequences of incomplete electrical test fault coverage and latent defects that become activated during the stress of normal operation is a major concern. Usually, for the sake of yield estimation, it is assumed that any defect detected electrically with a defect test structure leads to a circuit failure. However, there is a wide range of defects which cause performance degradation without causing failure. This paper discusses process-induced defects and the faults they cause in logic gates and focuses in more detail on bridging defects