A flexible pipelined image processor

Author

Kelly, Mike ; Hsu, Kenneth W.

Author_Institution

Dept. of Comput. Eng., Rochester Inst. of Technol., NY, USA

fYear

1998

fDate

13-16 Sep 1998

Firstpage

325

Lastpage

332

Abstract

This paper describes the design of a flexible, pipelined general image processor (GIP) using VHDL to model the top level design and functional blocks consisting of histogram modification, convolution, halftone, error diffusion, and threshold. The GIP was simulated to have a processing speed of 70 Mpixels/second. A four pixel wide image data path is used so a clock of 17.5 MHz can be used. Mentor Graphics tool suites were used to perform the simulation and synthesis of the design. The total number of gates in 1.2 μm CMOS gate array was estimated to be 236 K gates, less than 1 million transistors

Keywords

CMOS digital integrated circuits; VLSI; circuit CAD; convolution; digital signal processing chips; high level synthesis; image processing; image processing equipment; pipeline processing; 1.2 micron; 17.5 MHz; CMOS gate array; DSP chip; Mentor Graphics tool suites; VHDL modelling; convolution; error diffusion block; halftone block; histogram modification; pipelined image processor; threshold block; top level design; Clocks; Computational modeling; Computer errors; Convolution; Delay; Design engineering; Histograms; Microprocessors; Pipelines; Protocols;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-4980-6

Type

conf

DOI

10.1109/ASIC.1998.723026

Filename

723026