A new VLSI-oriented FFT algorithm and implementation

Author

Jia, Lihong ; Gao, Yonghong ; Isoaho, Jouni ; Tenhunen, Hannu

Author_Institution

Electron. Syst. Design Lab., R. Inst. of Technol., Stockholm, Sweden

fYear

1998

fDate

13-16 Sep 1998

Firstpage

337

Lastpage

341

Abstract

In this paper, we present a new VLSI-oriented fast Fourier transform (FFT) algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. This algorithm can be implemented efficiently using a pipelined architecture. Based on this pipelined architecture, an 8 K FFT ASIC is designed for use in the DVB (Digital Video Broadcasting) application in 0.6 μm-3.3 V triple-metal CMOS process

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; digital signal processing chips; digital video broadcasting; fast Fourier transforms; parallel algorithms; parallel architectures; pipeline arithmetic; video signal processing; 0.6 micron; 3.3 V; DSP chip; DVB application; FFT ASIC; VLSI-oriented FFT algorithm; digital video broadcasting application; fast Fourier transform; multiplications; pipelined architecture; triple-metal CMOS process; Algorithm design and analysis; Application specific integrated circuits; CMOS process; Digital video broadcasting; Fast Fourier transforms; Laboratories; Signal processing algorithms; Telecommunication standards; Very large scale integration; Video signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-4980-6

Type

conf

DOI

10.1109/ASIC.1998.723029

Filename

723029