Fast, accurate prediction of PLL jitter induced by power grid noise

Timing jitter caused by power supply fluctuations is an important concern in phase-locked loop (PLL) design. We present a novel technique for predicting supply-induced PLL timing jitter that is much more accurate than prior methods. Our method, based on a nonlinear VCO macromodel, is able to predict phase errors correctly where prior linear macromodels fail. The macromodel is easily extracted from SPICE-level descriptions of any oscillator or VCO. We demonstrate the proposed technique on a ring oscillator based PLL, providing comparisons against prior linear macromodels and against full spice-level simulations. Speedups of three orders of magnitude are obtained over full SPICE-level simulation, with larger speedups expected for PLLs with more devices and nodes.