• DocumentCode
    1947916
  • Title

    A Highly Reliable Gate/n- Overlapped Transistor for Mega-bit DRAMs

  • Author

    Nagatomo, M. ; Okumura, Y. ; Mitsui, K. ; Ogoh, I. ; Joh, H. Gen ; Inuishi, M. ; Matsukawa, T.

  • Author_Institution
    LSI R&D Laboratory, Mitsubishi Electric Corp., 4-1 Mizuhara, Itami, 664, JAPAN
  • fYear
    1989
  • fDate
    11-14 Sept. 1989
  • Firstpage
    923
  • Lastpage
    926
  • Abstract
    A noble gate/N- overlapped Tr. fabricated using oblique rotating ion implantation technique was developed. It is confirmed that this Tr. meets high performance M bit DRAMs´ requirements, that is, high drain current, enough punchthrough voltage and low substrate current. The mechanism of this Tr.´s action is analyzed by simulation and is concluded that peak position of electric field is located far from the drain current pass in this Tr.´s structure. The maximum electric field is also relaxed by formation of N- layer using oblique ion implantation.
  • Keywords
    Analytical models; Degradation; FETs; Impurities; Large scale integration; Parasitic capacitance; Performance analysis; Research and development; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid State Device Research Conference, 1989. ESSDERC '89. 19th European
  • Conference_Location
    Berlin, Germany
  • Print_ISBN
    0387510001
  • Type

    conf

  • Filename
    5437066
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1947916