Thermal stress simulation in the metal-insulator-metal (MIM) wafer fabrication process

Integrated passive technologies have obtained more and more attention due to the increasing demand for functional integration for cost, performance and size reasons. Integration of passive components such as capacitors into semiconductor devices drives a higher degree of system-level integration. Currently, integrated capacitors are fabricated by using metal-insulator-metal (MIM) structure. In the MIM capacitor fabrication process, the dielectrics, electrodes and final protection layer are deposited on the substrate, layer by layer, at different temperatures. This may generate thermal stress because of the deposition temperature changes. If the thermal stress is very high, as it may be for certain device layouts, it may even cause cracks in the dielectric layer due to the CTE mismatch of different layers. Therefore, in this paper, the MIM capacitor fabrication process is simulated to obtain the thermal stress in different layers and at different process stages. The effect of the parameters of a typical MIM structure is studied. Especially the impact of guard ring thickness, space or overlap of a polyimide layer and guard ring to bottom metal, space or overlap of between metal layers are thoroughly investigated. A total of 15 DoEs in reasonable parameter ranges are designed and conducted for the thermal stress simulation.