An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

Author

Williams, Stephen ; Thompson, Hugh ; Hufford, Michael ; Naviasky, Eric

Author_Institution

Cadence Design Services, Columbia, MD, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

151

Lastpage

154

Abstract

This paper describes a low jitter phase-locked-loop (PLL) with a 4^th order control path, and a dual control voltage ring oscillator. Near constant voltage controlled oscillator (VCO) gain over process variations, in addition to compensation for feedback ratio variation, allows improved control of the PLL bandwidth. The PLL exhibits improved noise immunity with a wide (5:1) VCO frequency range, without the need for band switching or calibration routines. This PLL is fabricated in a 0.18 μm CMOS logic process and exhibits <4 ps rms accumulated jitter.

Keywords

CMOS integrated circuits; UHF oscillators; circuit feedback; phase locked loops; timing jitter; voltage-controlled oscillators; 0.18 micron; 100 to 500 MHz; CMOS logic process; CMOS ring oscillator PLL; PLL bandwidth control; VCO frequency range; accumulated jitter; constant gain VCO; dual control voltage ring oscillator; feedback ratio variation compensation; low jitter phase-locked-loop; noise immunity; Bandwidth; CMOS process; Calibration; Feedback; Frequency; Jitter; Phase locked loops; Ring oscillators; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358761

Filename

1358761