Title :
A 625 MHz to 10 GHz clock multiplier for re-transmitting 10 Gb/s serial data
Author :
Yao, Chih-Wei ; Pham, Hiep T. ; Willson, Alan N., Jr.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
A low-jitter 10 GHz clock multiplier in 0.18-μm CMOS is presented. With 0.47 ps rms jitter (50 kHz-80 MHz) in a reference clock that approximates the quality of the clock recovered by a receiver, 0.33 ps rms output jitter is achieved with a 633-kHz loop. With a 120-kHz loop, that satisfies the SONET OC-192 jitter transfer mask, the output jitter is 0.57 ps rms.
Keywords :
CMOS integrated circuits; MMIC frequency convertors; driver circuits; frequency multipliers; timing jitter; voltage-controlled oscillators; 0.18 micron; 10 GHz; 10 Gbit/s; 120 kHz; 50 kHz to 80 MHz; 625 MHz; 633 kHz; CMOS; LC-VCO; SONET OC-192 jitter transfer mask; clock driver; low-jitter clock multiplier; output jitter; reference clock; serial data retransmission; Bandwidth; Circuit noise; Clocks; Jitter; MOS capacitors; Noise cancellation; Phase locked loops; Phase noise; SONET; Voltage-controlled oscillators;
Conference_Titel :
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN :
0-7803-8495-4
DOI :
10.1109/CICC.2004.1358762
