• DocumentCode
    1947955
  • Title

    Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps

  • Author

    Selvanayagam, Cheryl S. ; Lau, John H. ; Zhang, Xiaowu ; Seah, S.K.W. ; Vaidyanathan, Kripesh ; Chai, T.C.

  • Author_Institution
    Inst. of Microelectron., Agency for Sci., Technol., & Res., Singapore
  • fYear
    2008
  • fDate
    27-30 May 2008
  • Firstpage
    1073
  • Lastpage
    1081
  • Abstract
    Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5x10-6/degC) is a few times higher than that of silicon (~2.5x10-6/degC). Thus, when the copper filled TSV is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO2), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this study, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore´s (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10x10-6/degC. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without under- fills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for (1) making a decision if underfills are necessary for the reliability of microbumps, and (2) selecting underfill materials to minimize the stresses and strains in the microbumps.
  • Keywords
    copper; delamination; flip-chip devices; integrated circuit packaging; silicon; stress analysis; thermal analysis; thermal expansion; thermal management (packaging); Moore´s law; aspect ratios; copper filled TSV; delamination; flip-chip microbumps; nonlinear strains; nonlinear stresses; nonlinear thermal analysis; silicon chip; temperature loadings; thermal expansion coefficient; thermal expansion mismatch; through silicon via; Capacitive sensors; Copper; Dielectrics; Silicon; Temperature; Thermal expansion; Thermal loading; Thermal stresses; Through-silicon vias; Tungsten;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2008. ECTC 2008. 58th
  • Conference_Location
    Lake Buena Vista, FL
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4244-2230-2
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2008.4550108
  • Filename
    4550108