DocumentCode :
1948040
Title :
Extra link multistage interconnection network for packet switching
Author :
Somani, Arun K. ; Choi, Sang Bang
Author_Institution :
Fault Tolerant Comput. Lab., Washington Univ., Seattle, WA, USA
fYear :
1990
fDate :
21-23 Mar 1990
Firstpage :
893
Abstract :
Summary form only given. The authors focus on the design of networks for packet switching communication. They propose a general design method for high-performance fault-tolerant networks in this environment. To improve the performance and fault tolerance of multistage interconnection networks (MINs), redundant routing paths, are provided in a network with the help of some additional links. The authors have simulated the proposed networks, along with several others, and present simulation results under various realistic environments to support their claim of high performance with or without the presence of faults
Keywords :
fault tolerant computing; multiprocessor interconnection networks; packet switching; MINs; fault-tolerant networks; high-performance; multistage interconnection network; packet switching; redundant routing paths; Computer networks; Delay; Design methodology; Fault tolerance; Laboratories; Multiprocessor interconnection networks; Packet switching; Redundancy; Routing; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computers and Communications, 1990. Conference Proceedings., Ninth Annual International Phoenix Conference on
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-8186-2030-7
Type :
conf
DOI :
10.1109/PCCC.1990.101734
Filename :
101734
Link To Document :
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