DocumentCode
1948117
Title
Interconnect Design Strategy for High-Speed Logic LSIs
Author
Yamashina, Masakazu ; Mizuno, Masayuki ; Shibayama, Atsufumi
Author_Institution
NEC, Japan
Volume
1
fYear
1999
fDate
13-15 Sept. 1999
Firstpage
11
Lastpage
16
Keywords
CMOS logic circuits; Clocks; Delay estimation; Frequency; Integrated circuit interconnections; Large scale integration; Logic design; Technological innovation; Wire; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference, 1999. Proceeding of the 29th European
Conference_Location
Leuven, Belgium
Print_ISBN
2-86332-245-1
Type
conf
Filename
1505443
Link To Document