Minimal Instruction Set AES Processor using Harvard Architecture

This paper presents an FPGA implementation of Advance Encryption Standard (AES), using Minimal Instruction Set Computer (MISC) with Harvard Architecture. With simple logic components and a minimum set of fundamental instructions, the MISC using Harvard Architecture enables the AES encryption in severely constraint hardware environment, with lesser execution clock cycles. The MISC architecture was verified using the Handel-C hardware description language and implemented on a Xilinx Spartan3 FPGA. The implementation uses two separate block RAMs and occupied only 1% of the total available chip area.