Title :
Design-for-digital-testability 30 MHz second-order Σ-Δ modulator
Author_Institution :
Dept. of Electr. & Control Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Abstract :
A purely digitally testable second-order Σ-Δ modulator is presented. In the test mode, the input stage of the modulator is reconfigured to accept a repetitive Σ-Δ modulated bit-stream as its stimulus. The proposed test scheme has a low cost, a high fault coverage, high measurement accuracy, and is able to do the at-speed tests. The experimental results show that the dynamic range measured with the digital stimulus is only 2 dB inferior to that with its analog counterpart.
Keywords :
VHF circuits; built-in self test; design for testability; integrated circuit testing; sigma-delta modulation; 30 MHz; BIST; at-speed tests; design-for-digital-testability; digital stimulus; digitally testable modulator; fault coverage; measurement accuracy; measurement dynamic range; repetitive modulated bit-stream stimulus; second-order Σ-Δ modulator; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Costs; Delta modulation; Digital modulation; Integrated circuit measurements; Sequential analysis; System-on-a-chip;
Conference_Titel :
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN :
0-7803-8495-4
DOI :
10.1109/CICC.2004.1358779
