Title :
RFCMOS technology from 0.25μm to 65nm: the state of the art
Author :
Pekarik, J. ; Greenberg, D. ; Jagannathan, B. ; Groves, R. ; Jones, J.R. ; Singh, R. ; Chinthakindi, A. ; Wang, X. ; Breitwisch, M. ; Coolbaugh, D. ; Cottrell, P. ; Florkey, J. ; Freeman, G. ; Krishnasamy, R.
Author_Institution :
Semicond. Res. & Dev. Center, IBM, Essex Junction, VT, USA
Abstract :
The effort to design RF circuits in CMOS is motivated by low cost and significant capacity for on-chip integration. We discuss some of the challenges of implementing RF designs in CMOS, focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink. We present methods and tools, using which, designers can ease these challenges and reduce the risk of implementing RF circuits in CMOS.
Keywords :
CMOS integrated circuits; integrated circuit design; radiofrequency integrated circuits; 0.25 micron to 65 nm; CMOS RFIC; FET device shrinkage; RFCMOS technology; low cost RF circuits; on-chip integration capacity; technology node scaling; BiCMOS integrated circuits; CMOS process; CMOS technology; Costs; FETs; Radio frequency; Research and development; Semiconductor device modeling; Technological innovation; Varactors;
Conference_Titel :
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN :
0-7803-8495-4
DOI :
10.1109/CICC.2004.1358782
