Title :
A high speed CMOS buffer for driving large capacitive loads in digital ASICs
Author :
Secareanu, Radu M. ; Friedman, Eby G.
Author_Institution :
Dept. of Electr. Eng., Rochester Univ., NY, USA
Abstract :
A High Speed High-Drive (HD) CMOS buffer is described in this paper which is an alternative to the widely used CMOS tapered buffer. The paper introduces the principle of operation of the HD buffer and compares it with a tapered buffer. Depending upon the capacitive load, the HD buffer as compared to an equivalent tapered buffer can provide increased speed (up to 2.2×) or multiple speed/power/area trade-offs. Clock distribution networks, large data buses, and I/O buffers are some possible applications of this buffer structure
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; buffer circuits; capacitance; driver circuits; high-speed integrated circuits; I/O buffers; clock distribution networks; digital ASICs; high speed CMOS buffer; large capacitive load driving; large data buses; Application specific integrated circuits; Capacitance; Clocks; Conductivity; Dielectric constant; Dielectric materials; Digital circuits; High definition video; Logic circuits; Pulse inverters;
Conference_Titel :
ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International
Conference_Location :
Rochester, NY
Print_ISBN :
0-7803-4980-6
DOI :
10.1109/ASIC.1998.723037
