• DocumentCode
    1948433
  • Title

    ESD protection - Session 12

  • fYear
    2004
  • fDate
    6-6 Oct. 2004
  • Firstpage
    241
  • Lastpage
    241
  • Abstract
    Electrostatic discharge is a serious reliability problem for integrated circuits. As deep sub-micron technologies advance, the challenges of designing and implementing robust ESD protections have become more acute. Wire and diffusion resistance have increased with scaling. ESD sensitivity due to ultra-thin gate oxides has also increased, while the voltage needed to bias diodes into conduction has remained the same as previous technology generations. All of these issues bring to bear the need for design, simulation and analysis of ESD protections in deep sub-micron technologies.
  • Keywords
    Analytical models; CMOS technology; Circuit simulation; Electrostatic discharge; Integrated circuit reliability; Paper technology; Performance analysis; Power system protection; Predictive models; Robustness;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
  • Conference_Location
    Orlando, FL, USA
  • Print_ISBN
    0-7803-8495-4
  • Type

    conf

  • DOI
    10.1109/CICC.2004.1358786
  • Filename
    1358786