DocumentCode
1948453
Title
A 3D mixed-mode ESD protection circuit simulation-design methodology
Author
Xie, H. ; Zhan, R. ; Feng, H. ; Chen, G. ; Wang, Albert ; Gafiteanu, R.
Author_Institution
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
fYear
2004
fDate
3-6 Oct. 2004
Firstpage
243
Lastpage
246
Abstract
Electrostatic discharge (ESD) is a serious IC reliability problem. On-chip ESD protection is used to protect ICs against ESD damage. This paper presents a real 3D mixed-mode ESD protection circuit simulation-design methodology for ESD design prediction. Practical ESD protection design examples in 0.35 μm BiCMOS are given.
Keywords
BiCMOS integrated circuits; circuit simulation; electrostatic discharge; integrated circuit design; integrated circuit modelling; integrated circuit reliability; 0.35 micron; 3D mixed-mode ESD protection circuit; BiCMOS; ESD failures; IC reliability; circuit simulation-design methodology; electrostatic discharge; on-chip ESD protection; BiCMOS integrated circuits; Calibration; Circuit simulation; Circuit testing; Design methodology; Electrostatic discharge; Power system transients; Predictive models; Protection; Thermal resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN
0-7803-8495-4
Type
conf
DOI
10.1109/CICC.2004.1358788
Filename
1358788
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