Improving memory support in the VTR flow

VTR is an open source academic FPGA CAD flow designed for exploration of hypothetical FPGA architectures. High level language and architectural feature support are of continuing importance to researchers using the VTR flow to explore these architectures. In this paper we will discuss the extension of VTR to support implicit memories and the elaboration of explicit and implicit memories into soft logic, contributing to improved language support as well as available elaboration options for memories. The addition of full support for architecture-aware memory splitting and padding during elaboration is also detailed and validated which introduces a range of memory elaboration options which were previously not possible. This paper will also detail two experiments designed to validate and explore these new capabilities using the VTR flow. These experiments pave the way for further explorations using these new capabilities. Application of these new features to future architectural explorations will also be discussed.