M/sup 3/-a multilevel mixed-mode mixed D/A simulator

Author

Chadha, R. ; Chen, Chien-Fu

Author_Institution

AT&T Bell Lab., Murray Hill, NJ, USA

fYear

1988

fDate

7-10 Nov. 1988

Firstpage

258

Lastpage

261

Abstract

The method presented allows digital, analog and mixed D/A portions of a circuit to be described at behavioral, functional, cell, and transistor levels. The analog portions of the circuit are simulated with maximum accuracy while the digital portions are simulated in various modes. M/sup 3/ is event-driven and uses block elimination with unique reordering and pivoting techniques to accommodate state variables for behavioral analog or mixed D/A models. The simulator has been integrated into the MOTIS3 design verification system. A representative mixed D/A simulation example is included.<>

Keywords

analogue computer circuits; circuit analysis computing; digital circuits; digital-analogue conversion; M/sup 3/; MOTIS3 design verification system; behavioral analog; behavioral level; block elimination; circuit portion description; event-driven; mixed D/A models; mixed D/A portions; mixed D/A simulation example; multilevel mixed-mode mixed D/A simulator; pivoting techniques; state variables; transistor levels; unique reordering; Capacitance; Circuit simulation; Coupling circuits; Delay effects; Digital-analog conversion; Equations; Logic; MOSFETs; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1988. ICCAD-88. Digest of Technical Papers., IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-0869-2

Type

conf

DOI

10.1109/ICCAD.1988.122506

Filename

122506