DocumentCode
1948710
Title
Speedy bus mastering PCI express
Author
Bittner, Ray
Author_Institution
Microsoft Res., Redmond, WA, USA
fYear
2012
fDate
29-31 Aug. 2012
Firstpage
523
Lastpage
526
Abstract
PCI Express is a ubiquitous bus interface providing the highest bandwidth connection in the PC platform. Sadly, support for it in FPGAs is limited and/or expensive. The Speedy PCIe core addresses this problem by bridging the gap from the bare bones interface to a user friendly, high performance design. This paper describes some of the fundamental design challenges and how they were addressed as well as giving detailed results. The hardware and software source code are available for free download from [12].
Keywords
field programmable gate arrays; logic design; peripheral interfaces; FPGA; high performance design; speedy PCIe core; speedy bus mastering PCI express; ubiquitous bus interface; Bandwidth; Clocks; Field programmable gate arrays; Hardware; Operating systems; Protocols;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on
Conference_Location
Oslo
Print_ISBN
978-1-4673-2257-7
Electronic_ISBN
978-1-4673-2255-3
Type
conf
DOI
10.1109/FPL.2012.6339270
Filename
6339270
Link To Document