An improved architecture of the mixed mode clock/data recovery for DVD read channel

A mixed mode clock and data recovery module for DVD player and recorder is developed. The proposed system is the improved version of the conventional one which integrates an analog front end, a clock recovery circuit, and a partial response maximum likelihood (PRML) employing PR (1,2,2,1) channel model. For achieving a low-power, low-cost and high speed read-channel IC, the digital adaptive equalizer in the conventional DVD system is replaced with a waveform controller. Also, an analog charge-pump and external low pass filter (LPF) are employed instead of the digital LPF in the clock recovery loop for higher speed. The proposed architecture reduces power consumption and die size by 28.3% and 41.8%, respectively. Gain with the PRML technique is about 4 dB superior to that of a slicer at BER 10^-4. The chip has been fabricated with 0.18 μm one-poly five-metal CMOS technology.