Reliability of high-end flip-chip package with large 45nm ultra low-k die

The ultra low-K (ULK) dielectric material employed in 45 nm process technology is more porous and brittle than low-K dielectric used in prior generations. This paper looks into the effects of packaging materials on the reliability of a 42.5 times 42.5 mm flip-chip package assembled by a 20 times 20 mm ULK daisy chain die with 180 mum bump pitch and organic build-up thin-core substrate. Underfill materials with low T_g and high modulus, high T_g and high modulus, and high T_g and low modulus have been evaluated. In addition the effects of die thickness were studied. Finite element modeling, room temperature coplanarity, component-level and board-level temperature cycling tests have been used to study the different underfill materials and die thicknesses. Results show that room temperature warpage, propensity for ULK delamination, and solder joint reliability were significantly affected by the underfill properties.