A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond

Author

Komatsu, Yoshihide ; Arima, Yukio ; Fujimoto, Tetsuya ; Yamashita, Takahiro ; Ishibashi, Koichiro

Author_Institution

Semicond. Technol. Acad. Res. Center, Yokohama, Japan

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

329

Lastpage

332

Abstract

In this paper, we proposed a soft-error hardened latch (SEH-latch) scheme that has an error correction function in the fine process. To achieve this, we designed two types of SEH-latch circuits and a standard latch circuit using 130 nm 2-well, and also 90 nm 2-well CMOS processes. The proposed circuit demonstrated 2-order higher immunity through a radiation test using α-particles, and 1-order higher immunity through neutron irradiation.

Keywords

CMOS logic circuits; alpha-particle effects; error correction; flip-flops; integrated circuit design; integrated circuit testing; logic design; logic testing; neutron effects; system-on-chip; 130 nm; 90 nm; SEH-latch circuit design; SoC; alpha-particle irradiation; error correction function; fine process; neutron irradiation; radiation test; soft-error hardened latch scheme; soft-error immunity; standard latch circuit; two-well CMOS processes; CMOS process; Circuit testing; Error correction; Error correction codes; Latches; Logic circuits; MOS devices; Neutrons; Radiation hardening; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358812

Filename

1358812