Title :
BIST controlled variable sense amp timing for 90nm embedded SRAM
Author :
Brennan, C.J. ; Eustis, S. ; Goss, J. ; Humphrey, A. ; Ouellette, M. ; Rowland, J. ; Fragano, M.
Author_Institution :
IBM Microeletronics Div., Essex Junction, VT, USA
Abstract :
Embedded compilable SRAMs, using set sense amp (SSA) timing circuits with variable delays that can be selected during built-in self-test (BIST), are described. The primary purpose of the variable delays is to detect weak cells and AC defects during self test by reducing the "set sense-amp" (SSA) delay, and thereby reducing the signal margin. The weak cells can then be permanently replaced by redundant cells. The variable delay feature is also a powerful characterization tool for new array designs.
Keywords :
SRAM chips; amplifiers; built-in self test; delay circuits; redundancy; timing circuits; 90 nm; AC defects; BIST controlled variable sense amp timing; built-in self-test; embedded compilable SRAM; redundant cells; set sense amp timing circuits; set sense-amp delay; variable delays; weak cell detection; Application specific integrated circuits; Automatic testing; Built-in self-test; Circuit testing; Delay; Frequency; Random access memory; Signal design; Signal generators; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN :
0-7803-8495-4
DOI :
10.1109/CICC.2004.1358817
