Optimizing RC tree delay in high speed ASICs through repeater insertion

Author

Adler, Victor ; Friedman, Eby G.

Author_Institution

Dept. of Electr. Eng., Rochester Univ., NY, USA

fYear

1998

fDate

13-16 Sep 1998

Firstpage

375

Lastpage

379

Abstract

One method of overcoming wire delay due to long resistive interconnect is to insert repeaters in the line. Analytical expressions describing a CMOS inverter driving an RC load have been integrated into a global optimization algorithm for inserting repeaters into RC trees. The timing model predicts results generally within 10% of SPICE. The global optimization method exhibits total delay improvements of up to 86% over typical cascaded buffer insertion methods. The repeater timing model, global insertion methodology and algorithm, and software implementation are summarized in this paper

Keywords

CMOS digital integrated circuits; application specific integrated circuits; circuit CAD; circuit optimisation; delays; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; timing; CMOS inverter; RC load driving; RC tree delay optimisation; global insertion methodology; global optimization algorithm; high speed ASICs; long resistive interconnect; repeater insertion; repeater timing model; software implementation; wire delay; Algorithm design and analysis; Delay; Inverters; Optimization methods; Predictive models; Repeaters; SPICE; Semiconductor device modeling; Timing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC Conference 1998. Proceedings. Eleventh Annual IEEE International

Conference_Location

Rochester, NY

ISSN

1063-0988

Print_ISBN

0-7803-4980-6

Type

conf

DOI

10.1109/ASIC.1998.723041

Filename

723041