Architectural features of the i860-microprocessor RISC core and on-chip caches

Author

Patel, Piyush ; Douglass, Diane

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

1989

fDate

2-4 Oct 1989

Firstpage

385

Lastpage

390

Abstract

The Intel i860 is a one-million-transistor, high-performance RISC (reduced-instruction-set computer) microprocessor. The performance of the i860 CPU is derived using supercomputer architectural concepts such as parallel instruction execution and a 64-b architecture that provides the data and instruction bandwidth necessary to support multiple operations. The novel features of the i860 RISC integer core are explored. The on-chip cache architecture, which is optimized for large data and instruction bandwidth, is described

Keywords

microprocessor chips; reduced instruction set computing; Intel i860; RISC microprocessor; data bandwidth; i860 CPU; i860 RISC integer core; instruction bandwidth; multiple operations; on-chip cache architecture; parallel instruction execution; performance; reduced-instruction-set computer; supercomputer architectural concepts; Clocks; Computer aided instruction; Decoding; Delay; Graphics; Microprocessors; Performance loss; Pipeline processing; Reduced instruction set computing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on

Conference_Location

Cambridge, MA

Print_ISBN

0-8186-1971-6

Type

conf

DOI

10.1109/ICCD.1989.63393

Filename

63393