Title :
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules
Author :
Farmahini-Farahani, Amin ; Jung Ho Ahn ; Morrow, Katherine ; Nam Sung Kim
Author_Institution :
Univ. of Wisconsin-Madison, Madison, WI, USA
Abstract :
Energy consumed for transferring data across the processor memory hierarchy constitutes a large fraction of total system energy consumption, and this fraction has steadily increased with technology scaling. In this paper, we propose near-DRAM acceleration (NDA) architectures, which process data using accelerators 3D-stacked on DRAM devices comprising off-chip main memory modules. NDA transfers most data through high-bandwidth and low-energy 3D interconnects between accelerators and DRAM devices instead of low-bandwidth and high-energy off-chip interconnects between a processor and DRAM devices, substantially reducing energy consumption and improving performance. Unlike previous near-memory processing architectures, NDA is built upon commodity DRAM devices; apart from inserting through-silicon vias (TSVs) to 3D-interconnect DRAM devices and accelerators, NDA requires minimal changes to the commodity DRAM device and standard memory module architectures. This allows NDA to be more easily adopted in both existing and emerging systems. Our experiments demonstrate that, on average, our NDA-based system consumes 46% (68%) lower (data transfer) energy at 1.67× higher performance than a system that integrates the same accelerator logic within the processor itself.
Keywords :
DRAM chips; energy consumption; three-dimensional integrated circuits; NDA architectures; TSV; accelerator 3D-stack; accelerator logic; data processing; data transfer; high-bandwidth 3D interconnection; leveraging commodity DRAM devices; low-energy 3D interconnection; near-DRAM acceleration architecture; near-memory processing architectures; off-chip main memory modules; performance improvement; processor memory hierarchy; standard memory modules; through-silicon vias; total system energy consumption reduction; Bandwidth; Computer architecture; Data transfer; Microarchitecture; Performance evaluation; Random access memory; Through-silicon vias;
Conference_Titel :
High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on
Conference_Location :
Burlingame, CA
DOI :
10.1109/HPCA.2015.7056040