Title :
A high performance CMOS programmable logic core
Author :
Han, Yi ; Mcmurchie, Larry ; Sechen, Carl
Author_Institution :
Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
Abstract :
Programmable logic cores (PLCs) have become available for systems on a chip (SOCs). We describe a novel highspeed PLC architecture. By combining a high-performance dynamic logic style (output prediction logic or OPL), wired-OR structures, a unidirectional routing flow and a product-term-based structure, this architecture achieves an average speedup of 5.7 times over commercial look-up-table (LUT) based architectures using static CMOS. Experimental results for a prototype block fabricated in the TSMC 0.18 μm/1.8 V CMOS process are presented.
Keywords :
CMOS logic circuits; high-speed integrated circuits; integrated circuit testing; logic testing; network routing; programmable logic devices; system-on-chip; 0.18 micron; 1.8 V; CMOS programmable logic core; OPL; SOC; TSMC CMOS process; high-performance dynamic logic style; high-speed PLC architecture; look-up-table based architectures; output prediction logic; product-term-based structure; prototype block; static CMOS; system on chip; unidirectional routing flow; wired-OR structures; CMOS logic circuits; Delay; Field programmable gate arrays; Logic circuits; Multiplexing; Programmable control; Programmable logic arrays; Programmable logic devices; Routing; System-on-a-chip;
Conference_Titel :
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN :
0-7803-8495-4
DOI :
10.1109/CICC.2004.1358845
