• DocumentCode
    1949732
  • Title

    SCOC: High-radix switches made of bufferless clos networks

  • Author

    Chrysos, Nikolaos ; Minkenberg, Cyriel ; Rudquist, Mark ; Basso, Claude ; Vanderpool, Brian

  • Author_Institution
    IBM Res., Zurich, Switzerland
  • fYear
    2015
  • fDate
    7-11 Feb. 2015
  • Firstpage
    402
  • Lastpage
    414
  • Abstract
    In today´s datacenters handling big data and for exascale computers of tomorrow, there is a pressing need for high-radix switches to economically and efficiently unify the computing and storage resources that are dispersed across multiple racks. In this paper, we present SCOC, a switch architecture suitable for economical IC implementation that can efficiently replace crossbars for high-radix switch nodes. SCOC is a multi-stage bufferless network with O(N2/m) cost, where m is a design parameter, practically ranging between 4-16. We identify and resolve more than five fairness violations that are pertinent to hierarchical scheduling. Effectively, from a performance perspective, SCOC is indistinguishable from efficient flat crossbars. Computer simulations show that it competes well or even outperforms flat crossbars and hierarchical switches. We report data from our ASIC implementation at 32 nm of a SCOC 136×136 switch, with shallow buffers, connecting 25 Gb/s links. In this first incarnation, SCOC is used at the spines of a server-rack, fat-tree network. Internally, it runs at 9.9 Tb/s, thus offering a speedup of 1.45 ×, and provides a fall-through latency of just 61 ns.
  • Keywords
    application specific integrated circuits; circuit complexity; hypercube networks; multistage interconnection networks; processor scheduling; switches; ASIC implementation; SCOC; big data handling; bufferless Clos networks; computer simulations; computing resources; datacenters; design parameter; economical IC implementation; exascale computers; fairness violations; fall-through latency; flat crossbars; hierarchical scheduling; hierarchical switches; high-radix switch nodes; multistage bufferless network; server-rack fat-tree network; shallow buffers; storage resources; switch architecture; Clocks; Computer architecture; Ports (Computers); Scheduling; System-on-chip; Topology; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Computer Architecture (HPCA), 2015 IEEE 21st International Symposium on
  • Conference_Location
    Burlingame, CA
  • Type

    conf

  • DOI
    10.1109/HPCA.2015.7056050
  • Filename
    7056050