Advanced ternary CAM circuits on 0.13 μm logic process technology

Author

Roth, Alan ; Foss, Dick ; McKenzie, Robert ; Perry, Douglas

Author_Institution

MOSAID Technol., Inc., Kanata, Ont., Canada

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

465

Lastpage

468

Abstract

An embedded ternary CAM macro derived from a 9M stand alone part with die size of 148 mm² uses a novel 3.542 μm² SRAM half-cell on a standard 0.13 μm logic process. In the embedded form it takes 13 mm²/Mbit. The macro achieves 166 M-searches/s with low power, under 0.5 W/Mbit. A divided match line greatly reduces the power inherent in parallel searches. Prioritized multiple match output, status bit functions, and on-the-fly variable word width are included.

Keywords

CMOS memory circuits; SRAM chips; content-addressable storage; embedded systems; integrated circuit design; logic design; memory architecture; 0.13 micron; CAM redundancy; CMOS; SRAM half-cell; die size; divided match line; embedded ternary CAM macro; inherent parallel search power; logic process technology; low power macro; on-the-fly variable word width; prioritized multiple match output; standard logic process; status bit functions; CADCAM; Capacitance; Circuit synthesis; Computer aided manufacturing; Energy consumption; Impedance matching; Logic circuits; Multivalued logic; Random access memory; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358852

Filename

1358852