• DocumentCode
    1949939
  • Title

    A validation method for parasitic capacitance extraction

  • Author

    Bennebroek, M.T. ; Klaassen, D.B.M.

  • Author_Institution
    Philips Research Laboratories, Eindhoven, The Netherlands
  • Volume
    1
  • fYear
    1999
  • fDate
    13-15 Sept. 1999
  • Firstpage
    448
  • Lastpage
    451
  • Keywords
    Circuit simulation; Circuit testing; Delay lines; Design automation; Integrated circuit interconnections; Integrated circuit layout; Oscillators; Parasitic capacitance; Pulse width modulation inverters; Space technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Device Research Conference, 1999. Proceeding of the 29th European
  • Conference_Location
    Leuven, Belgium
  • Print_ISBN
    2-86332-245-1
  • Type

    conf

  • Filename
    1505536
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1949939