Title :
A validation method for parasitic capacitance extraction
Author :
Bennebroek, M.T. ; Klaassen, D.B.M.
Author_Institution :
Philips Research Laboratories, Eindhoven, The Netherlands
Keywords :
Circuit simulation; Circuit testing; Delay lines; Design automation; Integrated circuit interconnections; Integrated circuit layout; Oscillators; Parasitic capacitance; Pulse width modulation inverters; Space technology;
Conference_Titel :
Solid-State Device Research Conference, 1999. Proceeding of the 29th European
Conference_Location :
Leuven, Belgium
Print_ISBN :
2-86332-245-1
