Performance limitation of on-chip global interconnects for high-speed signaling

This paper discusses performance limitations of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires are studied. However, the limitations of on-chip interconnects has not been studied sufficiently. This paper reveals the maximum performance of on-chip global interconnects, based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening, both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.