Analysis of coupling noise and it´s scalability in dynamic circuits [dynamic logic CMOS ICs]

Author

Chowdhury, Masud H. ; Ismail, Yehea I.

Author_Institution

Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

505

Lastpage

508

Abstract

The usage of noise sensitive dynamic circuits has become commonplace due to speed and area requirements, making the noise issue even more prominent. This paper focuses on the trends of coupling and its effects on dynamic circuits. The paper presents closed form analytical solutions for noise as well as noise tolerance metrics for dynamic circuits. These solutions are within 5% of dynamic simulations. It is shown that not all scaling trends are negative for noise, and that the scaling down of supply voltage and increasing frequency help improve certain aspects of the noise immunity of dynamic circuits. Most of the work treats the noise immunity and the noise content separately. This paper introduces an analysis of noise scalability by looking at the noise immunity and the noise content simultaneously.

Keywords

CMOS logic circuits; coupled circuits; integrated circuit modelling; integrated circuit noise; coupling noise; dynamic circuit scaling; dynamic logic CMOS IC; noise immunity; noise sensitive circuits; noise tolerance; supply voltage scaling; CMOS logic circuits; CMOS technology; Capacitance; Circuit noise; Circuit simulation; Conductors; Coupling circuits; Integrated circuit noise; Scalability; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358868

Filename

1358868