Linearity enhancement techniques in low OSR, high clock rate multi-bit continuous-time sigma-delta modulators

Author

Paton, Susana ; Poscher, T. ; Di Giandomenico, Antonio ; Kolhau, Klaus ; Hernandez, Luis ; Wiesbauer, Andreas ; Clara, Martin ; Frutos, Ramon

Author_Institution

Univ. Carlos III, Madrid, Spain

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

527

Lastpage

530

Abstract

This paper evaluates two techniques to improve the linearity of the main feedback D/A converter in multi-bit continuous-time sigma-delta modulators (CT-SDM). A self-calibrated current-steering (SCCS) implementation of the D/A converter is compared to the usage of a data-weighted averaging (DWA) algorithm on the selection of uncalibrated D/A-elements. Two test-chips including the two different solutions are presented and measurement results are compared. Clocked at 300 MHz, the two CT-SDMs achieve a dynamic range of 67 dB (DWA) and 70 dB (SCCS), respectively, over an analog bandwidth of 15 MHz.

Keywords

CMOS integrated circuits; circuit feedback; digital-analogue conversion; linearisation techniques; sigma-delta modulation; 15 MHz; 300 MHz; CMOS; CT-SDM; continuous-time sigma-delta modulators; data-weighted averaging algorithm; feedback D/A converter; high clock rate modulators; linearity enhancement techniques; low OSR modulators; multibit quantizers; multibit sigma-delta modulators; over-sampling ratio; self-calibrated current-steering implementation; Added delay; Bandwidth; Circuit testing; Clocks; Delta-sigma modulation; Dynamic range; Feedback; Linearity; Modulation coding; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358875

Filename

1358875