Coupling noise analysis and high frequency design optimization of power/ground plane stack-up in embedded chip substrate cavities

Future electronic systems demand faster, smaller, lighter and thinner products. Embedding active and passive components in package size boards is one of the major steps in accomplishing system level miniaturization and multifunctionality. All multifunctional system packages should pay attention to signal and power integrity for ensuring proper operation of the system. Predominant challenge encountered with respect to power integrity in mixed signal systems is coupling through the power distribution network. This coupling which is a form of noise affects power integrity if left unchecked, especially in case of embedded actives where there are large apertures (die sized) in the metal planes and cavities in dielectric to accommodate the chips. This paper for the first time brings out coupling noise analysis for different power/ground plane stack-ups in embedded chip substrate cavities.