Crack growth-resistant interconnects for high-reliability microelectronics

In order to improve the reliability of microelectronics packages and systems, designers are looking for ways to enhance the structural integrity of the interconnects. Area- array interconnects, such as flip-chip bumps at the first level and a ball grid array (BGA) at the second level, are currently the most popular choice, as they provide the highest density, as well as the best electrical performance. Solder, with or without lead, is the predominant material used to form this interconnect. The main failure mode for area-array interconnects is either cracking or delamination. The crack growth is typically driven by low cycle fatigue failure, in part due to appreciable creep in solder. Sometimes, delamination of the interconnect from the under bump metallization (UBM) is observed. The traditional approach to solve this problem has been to use a high modulus, high Tg and low CTE underfill at the first level, and compliant packaging and underfill at the second level. [I. Mohammed, et al., 2001] With the advent of silicon chips with low K material, which is quite fragile, the trend is moving towards using lower modulus and lower Tg underfill, which has put the stress back on the interconnects. Therefore, a new approach is needed to increase the robustness of the interconnects to allow for other advances such as finer pitch and low K dielectrics. In this paper, a modification to the copper pad design is considered to determine if it will improve the crack resistance. Three different truncated cone-shaped pads on both the silicon chip and the substrate are considered. The overall analysis was driven by a global model under thermal cycling. The solder was modeled with a damage initiation and evolution model, in addition to temperature dependent elastic and plastic properties. The damage evolution was captured through degradation and eventual removal of elements. In this way, the "crack" propagation around the copper pads was observed. The life expectancy as well as the dam- age dissipation energy was plotted for all the cases. The results showed a clear improvement in life expectancy with the modified copper pads, thereby proving the hypothesis that it is possible to increase the crack resistance of the interconnects. The damage dissipation energy also showed similar trends. There was also an optimal size for the copper pads as the case with the largest pad sizes for both the chip and the substrate showed a lower than optimal value. More work needs to be done to further quantify the increase in the life expectancy of the interconnects under both thermal and mechanical loadings. The areas of improvement include more accurate damage initiation and evolution models for solder, more detailed modeling of the interconnect structure, and doing the simulation with a lower mass scaling factor.