The performance and experimental results of a multiple bit rate symbol timing recovery circuit for PSK receivers

Author

Yuce, Mehmet R. ; Liu, Wentai ; Bharat, Bhaskar ; Damiano, John ; Franzon, Paul D.

Author_Institution

Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

591

Lastpage

594

Abstract

A low-power all-digital symbol timing recovery circuit for digital PSK transmission systems is implemented in a 0.35-μm silicon on insulator (SOI) technology. The symbol timing circuit is designed for a wide range of bit rates (0.1-100 kbps) and robust against fast and large Doppler shift or frequency error on the input signal. The system is therefore well-suited for receivers in deep-space and satellite applications. It is synchronized within 3 or 4 bits and the total power dissipation of the circuit is only 310 μW.

Keywords

CMOS digital integrated circuits; Doppler shift; low-power electronics; phase shift keying; radio receivers; satellite links; silicon-on-insulator; space communication links; synchronisation; 0.1 to 100 kbit/s; 0.35 micron; 2 V; 310 muW; Doppler shift; SOI CMOS; Si-SiO₂; deep-space receivers; digital PSK receivers; digital PSK transmission systems; input signal frequency error; low-power all-digital symbol timing recovery circuit; multiple bit rate symbol timing recovery circuit; satellite receivers; space communications; Bit rate; Circuits; Doppler shift; Frequency; Phase shift keying; Robustness; Satellites; Signal design; Silicon on insulator technology; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358893

Filename

1358893