DocumentCode
1950597
Title
An image recognition processor using dynamically reconfigurable ALU
Author
Miyamoto, Naoto ; Kotani, Koji ; Maruo, K. ; Ohmi, Tadahiro
Author_Institution
Graduate Sch. of Eng., Tohoku Univ., Sendai, Japan
fYear
2004
fDate
3-6 Oct. 2004
Firstpage
599
Lastpage
602
Abstract
An image recognition processor, utilizing a phase only correlation (POC) algorithm is proposed. The arithmetic logical unit (ALU) in this processor can be re-configured dynamically. By arranging the POC algorithm to a form suitable for reconfigurable computing, the proposed processor can perform 2D 512×512 pixel image recognition within 105.2 ms and using 310.9 mW of power. This power consumption is 11.3 times lower than that of a previously reported work with same execution time.
Keywords
digital arithmetic; digital signal processing chips; image recognition; optical correlation; reconfigurable architectures; 105.2 ms; 262144 pixel; 2D image recognition processor; 310.9 mW; 512 pixel; arithmetic logical unit; dynamically reconfigurable ALU; phase only correlation algorithm; reconfigurable computing; Arithmetic; Circuits; Computer architecture; Decoding; Frequency domain analysis; Image recognition; Image reconstruction; Pixel; Resource management;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004
Print_ISBN
0-7803-8495-4
Type
conf
DOI
10.1109/CICC.2004.1358895
Filename
1358895
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