A DC-10GHz linear-in-dB attenuator in 0.13 μm CMOS technology

Author

Dogan, Hakan ; Meyer, Robert G. ; Niknejad, Ali M.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

609

Lastpage

612

Abstract

A CMOS attenuator has been designed and fabricated in a commercial 0.13 μm CMOS process. Two Π stages are cascaded to achieve more than 35 dB of maximum attenuation over a frequency range of DC to 10 GHz. Minimum insertion loss varies from 0.8 dB at DC to 3 dB at 10 GHz and remains less than 2 dB in the frequency band of DC-4 GHz. Attenuation is achieved with a control voltage that varies from 0 V to 1.2 V and it is linear-in-dB with respect to the control voltage. A DC feedback loop is implemented to achieve input and output impedance matching over the frequency of interest.

Keywords

CMOS analogue integrated circuits; attenuators; cascade networks; circuit feedback; impedance matching; 0 Hz to 10 GHz; 0 to 1.2 V; 0.13 micron; 0.8 to 3 dB; 35 dB; CMOS; DC feedback loop; attenuation control voltage; cascaded Π stages; input impedance matching; insertion loss; linear-in-dB attenuator; output impedance matching; Attenuation; Attenuators; CMOS technology; Capacitors; Feedback loop; Impedance; Insertion loss; Network topology; Resistors; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358899

Filename

1358899