Performance analysis of fully-adaptable CRC accelerators on an FPGA

We present a methodology for designing high-speed fully-adaptable Cyclic Redundancy Check (CRC) accelerators capable of supporting wide range of CRC standards. We extend our previous research with a module for generating contents of look-up tables, and we design new overlapped pipelined architecture. The resulting integration requires minimal resource and it ensures fast table re-generating process. Our accelerators achieve highest throughput when compared to related work, with possibility of additionally increasing throughput by extending the number of bits processed at a time. On the Xilinx Virtex 6 LX550T board they occupy between 1-2% area to produce maximum of 289.8Gbps with BRAM, or between 1.6 - 14% of area for 418.8Gbps without BRAM.