Title :
New three dimensional (3D) memory array architecture for future ultra high density DRAM
Author :
Endoh, K. ; Sakuraba, H. ; Shinmei, K. ; Masuoka, F.
Author_Institution :
Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
Abstract :
A three dimensional (3D) memory array architecture is realized by stacking several cells in series vertically up on each cell which is located in two dimensional (2D) array matrix. Total bit-line capacitance of this proposed architecture´s DRAM is suppressed to 37% of normal DRAM, when one bit-line has 1 K-bit cells and the same design rules are used. Moreover, array area of 1 M-bit DRAM using the proposed architecture, is reduced to 11.5% of normal DRAM using the same design rules
Keywords :
DRAM chips; capacitance; cellular arrays; memory architecture; 1 Mbit; 2D array matrix; 3D memory array architectur; array area reduction; total bit-line capacitance reduction; ultra high density DRAM; vertically-stacked cells; Capacitors; Decoding; Equivalent circuits; Memory architecture; Random access memory; Registers; Signal restoration; Stacking;
Conference_Titel :
Microelectronics, 2000. Proceedings. 2000 22nd International Conference on
Conference_Location :
Nis
Print_ISBN :
0-7803-5235-1
DOI :
10.1109/ICMEL.2000.838729
