DocumentCode :
1951122
Title :
Variability aware support vector machine based macromodels for statistical estimation of subthreshold leakage power
Author :
Garg, Lokesh ; Sahula, Vineet
Author_Institution :
Dept. of ECE, Malviya Nat. Inst. of Technol. Jaipur, Jaipur, India
fYear :
2012
fDate :
19-21 Sept. 2012
Firstpage :
253
Lastpage :
256
Abstract :
In this paper, we present an accurate and efficient stack based macromodel for statistical subthreshold leakage power characterization of cmos gates. Our methodology is based on first characterizing the leakage power of basic stacks and then estimating the subthreshold leakage power of gates based on these stacks. We develop support vector machine (SVM) based macromodels to characterize the transistor stacks of cmos gates, while accounting the combined effect of process variation in length (L), threshold voltage (Vth), oxide thickness (Tox), supply voltage (0.6v-1.2v), temperature (0°C-100°C) and width (45nm-200nm) scalable at the same time. Our experiments show that we only need 30 stack models to predict the subthreshold leakage power of 7 basic gates across 58 input combinations. SVM based models have the ability to predict the leakage power with maximum average error of less than 0.634% in mean for 4 input NOR gate and maximum average error of 1.952% in standard deviation for 3 input NOR gate. Our results also show that there is on the average 17× improvement in runtime for estimating the mean and standard deviation of leakage power of a gate with 5000 Monte Carlo simulations.
Keywords :
CMOS logic circuits; MOSFET; Monte Carlo methods; circuit analysis computing; integrated circuit modelling; logic gates; statistical analysis; support vector machines; CMOS gates; Monte Carlo simulations; NOR gate; SVM based models; mean deviation estimation; size 45 nm to 200 nm; stack based macromodel; standard deviation estimation; statistical estimation; statistical subthreshold leakage power characterization; subthreshold leakage power; temperature 0 degC to 100 degC; transistor stacks; variability aware support vector machine based macromodels; voltage 0.6 V to 1.2 V; Logic gates; MOS devices; Mathematical model; SPICE; Support vector machines; Training; Transistors; Probability density function (pdf); Process variation; Subthreshold leakage power; Support Vector Machine (SVM);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-0685-0
Type :
conf
DOI :
10.1109/SMACD.2012.6339387
Filename :
6339387
Link To Document :
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