Low leakage circuit design for FPGAs

Author

Ciccarelli, Luca ; Lodi, Andrea ; Canegallo, Roberto

Author_Institution

Adv. Res. Center on Electron. Syst., Bologna Univ., Italy

fYear

2004

fDate

3-6 Oct. 2004

Firstpage

715

Lastpage

718

Abstract

Reconfigurable computing is well suited for wireless applications because of its capability to adapt to changing communication protocols. However, as technology scales, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. This paper presents different buffered switches mixing low and high threshold transistors which trade some delay performance to reduce by two orders of magnitude the leakage current of the switch blocks which generate most of the dissipation in FPGAs.

Keywords

buffer circuits; field programmable gate arrays; integrated circuit design; leakage currents; logic design; low-power electronics; FPGA scaling; buffered switches; communication protocols; inactive transistor leakage energy consumption; low leakage circuit design; mixed low/high threshold transistors; power consumption/propagation delay trade-off; reconfigurable computing; Circuit synthesis; Communication switching; Delay; Energy consumption; Field programmable gate arrays; Leakage current; Silicon; Switches; Threshold voltage; Wireless application protocol;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004

Print_ISBN

0-7803-8495-4

Type

conf

DOI

10.1109/CICC.2004.1358929

Filename

1358929