A half-micron super self-aligned BiCMOS technology for high speed applications

Author

Liu, T.M. ; Chin, Gillian M. ; Jeon, D.Y. ; Morris, M.D. ; Archer, V.D. ; Kim, H.H. ; Cerullo, M. ; Lee, K.F. ; Sung, J.M. ; Lau, K. ; Chiu, T.Y. ; Voshchenkov, A.M. ; Swartz, R.G.

Author_Institution

AT&T Bell Labs., Holmdel, NJ, USA

fYear

1992

fDate

13-16 Dec. 1992

Firstpage

23

Lastpage

26

Abstract

We report the process design, device characteristics and circuit performance of a new ultra high speed, high density, half-micron super self-aligned BiCMOS technology. The minimum CMOS gate delay was measured to be 38 psec on 0.5 mu m gate and 50 psec on 0.6 mu M gate ring oscillators at 5 volt. Bipolar gate delay was measured to be 31 psec on a 0.6 mu m emitter ECL ring oscillator. A single phase decision circuit operating error free at 8 Gb/sec and a static frequency divider operating above 10 Gb/sec were demonstrated in our BiCMOS technology.<>

Keywords

BiCMOS integrated circuits; delays; emitter-coupled logic; integrated circuit technology; integrated logic circuits; 0.5 micron; 0.6 micron; 10 Gbit/s; 31 ps; 38 ps; 5 V; 50 ps; 8 Gbit/s; ECL; bipolar gate delay; circuit performance; device characteristics; high speed applications; minimum CMOS gate delay; process design; ring oscillators; single phase decision circuit; static frequency divider; super self-aligned BiCMOS technology; BiCMOS integrated circuits; Delay effects; Emitter coupled logic; Integrated circuit fabrication;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International

Conference_Location

San Francisco, CA, USA

ISSN

0163-1918

Print_ISBN

0-7803-0817-4

Type

conf

DOI

10.1109/IEDM.1992.307300

Filename

307300