DocumentCode :
1951257
Title :
Gate insulating layer impact on the extension profile of the sub-50 nm p-MOSFET
Author :
Fukutome, H. ; Arimoto, H. ; Watanabe, S. ; Ohta, H. ; Hori, M.
Author_Institution :
Fujitsu Labs. Ltd., Tokyo, Japan
fYear :
2002
fDate :
2-3 Dec. 2002
Firstpage :
43
Lastpage :
46
Abstract :
The gate insulating layer impact on the extension profiles of the sub-50 nm p-MOSFETs is evaluated by direct visualization with the use of STM. The variation in the overlap between the gate electrode and the extension is measured. This variation is qualitatively consistent with that expected from the roll-off characteristics. Based on the results, it is considered that the horizontal extension profile strongly depends on the stress near the Si/SiON interface. It is also indicated that the insulating layer strongly affects on the horizontal abruptness of the junction near the Si/SiON interface.
Keywords :
MOSFET; elemental semiconductors; scanning tunnelling microscopy; silicon; silicon compounds; 50 nm; STM; Si-SiON; Si/SiON interface; direct visualization; gate electrode; gate insulating layer impact; p-MOSFET; scanning tunneling microscopy; Amorphous materials; Electrodes; Insulation; Laboratories; MOSFET circuits; Microscopy; Spectroscopy; Stress; Tunneling; Visualization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Junction Technology, 2002. IWJT. Extended Abstracts of the Third International Workshop on
Conference_Location :
Tokyo, Japan
Print_ISBN :
4-89114-028-3
Type :
conf
DOI :
10.1109/IWJT.2002.1225198
Filename :
1225198
Link To Document :
بازگشت