Title :
A high speed SOI technology with 12 ps/18 ps gate delay operating at 5 V/1.5 V
Author :
Jian Chen ; Parke, S. ; King, J. ; Assaderaghi, F. ; Ko, P.K. ; Chenming Hu
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
A high speed Silicon-on-Insulator technology was developed, and a high performance circuit operating at very low power supply voltages was realized. The SOI MOSFETs fabricated on ultra-thin SOI film are fully-depleted and demonstrate excellent short channel behavior. At power supply voltage of V/sub DD/=1.5 V and room temperature, typical propagation delay of 18 ps/stage was obtained for depletion-mode NMOS inverter ring oscillator. The best result shows delay time of 14 ps/stage at V/sub DD/=1.5 V for ring oscillator fabricated on 500 AA SOI film with T/sub ox/=70 AA. This are the best results reported for power supply voltage of 1.5 V at room temperature.<>
Keywords :
CMOS integrated circuits; integrated circuit technology; logic gates; semiconductor-insulator boundaries; 1.5 V; 12 ps; 18 ps; 5 V; CMOS technology; delay time; depletion-mode NMOS inverter ring oscillator; gate delay; high speed SOI technology; power supply voltages; propagation delay; short channel behavior; ultra-thin SOI film; CMOS integrated circuits; Integrated circuit fabrication; Semiconductor-insulator interfaces;
Conference_Titel :
Electron Devices Meeting, 1992. IEDM '92. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-0817-4
DOI :
10.1109/IEDM.1992.307303
